1. Field of the Invention
The present invention relates to a semiconductor memory, and particularly a semiconductor memory that has the redundancy repair function for repairing a defective memory cell.
2. Description of the Related Art
Highly integrated semiconductor memories, such as a static random access memory (SRAM) and a dynamic random access memory (DRAM), include a redundancy repair circuit to improve manufacturing yields. When a defective memory cell is present in a memory cell array of a semiconductor memory manufactured, the memory cell row or column that includes the defective memory cell is replaced functionally by a predetermined spare redundant memory cell row or column. This replacement of the memory cell row or column that includes a defective memory cell by the redundant memory cell row or column is known as redundancy repair function and can be used in general semiconductor memories such as SRAM and DRAM. The following is an explanation of an example of SRAM having the redundancy repair function.
FIG. 8 is a block diagram showing the configuration of a conventional semiconductor memory 90. The semiconductor memory 90 is formed as a SRAM. In FIG. 8, the SRAM includes a row redundancy repair signal generator 1 that generates a redundancy repair signal in accordance with the recorded information of a defective memory cell address by selectively disconnecting fuses.
The semiconductor memory 90 is provided with a SRAM macro 80. The SRAM macro 80 includes a memory cell array 2. The memory cell array 2 includes n (n is an integer not less than 2) memory cell rows, and each of the memory cell rows includes m (m is an integer not less than 2) memory cells 4 arranged in the row direction at predetermined intervals. The memory cell array 2 also includes at least one redundant memory cell row 7 for repairing a defective memory cell row of the n memory cell rows that includes a defective memory cell 5, and the redundant memory cell row 7 includes m redundant memory cells 6 arranged in the row direction at predetermined intervals.
In the memory cell array 2, n word lines WLa(0), . . . , WLa(n−1) are arranged in the row direction for each of the n memory cell rows, and at least one word line WLa(r) (r is an integer not less than 1) is arranged in the row direction for each of the at least one redundant memory cell row 7.
In the memory cell array 2, m complementary bit line pairs BLa(0)/NBLa(0), . . . , BLa(m−1)/NBLa(m−1) are arranged in the column direction for each of the m memory cell columns.
The row redundancy repair signal generator 1 is located next to the SRAM macro 80 and includes a plurality of fuses (not shown) that are disconnected selectively to store the address of the defective memory cell 5. According to the address stored in the fuses, the row redundancy repair signal generator 1 generates a redundancy repair signal that indicates the address of a defective memory cell row including the defective memory cell 5.
In the SRAM macro 80, a row decoder 3 is located between the memory cell array 2 and the row redundancy repair signal generator 1. The row decoder 3 receives a row address signal that indicates a memory cell row including a memory cell to be accessed and selects the word line WLa(r) in accordance with the redundancy repair signal generated by the row redundancy repair signal generator 1.
The SRAM macro 80 includes a data I/O circuit 12. The data I/O circuit 12 is provided with a column decoder 9. The column decoder 9 selects any of the complementary bit line pairs BLa(0)/NBLa(0), . . . , BLa(m−1)/NBLa(m−1) in accordance with a column address signal that indicates a memory cell column including a memory cell to be accessed. The data I/O circuit 12 writes data into a memory cell selected by the row decoder 3 and the column decoder 9 or reads data from the selected memory cell.
The SRAM macro 80 includes a control circuit 11. The control circuit 11 controls the operations of the row decoder 3 and the data I/O circuit 12 provided with the column decoder 9.
The operations of the semiconductor memory 90 having the above configuration will be described. First, the following is an explanation of the operation in which a non-defective memory cell 4 is specified by an externally input row address signal and column address signal.
Upon receiving a row address signal, the row decoder 3 selects a word line WLa(j) for the non-defective memory cell 4 in accordance with the row address signal. The memory cell 4 that corresponds to the word line WLa(j) is connected electrically to a bit line pair BLa(i)/NBLa(i). The column decoder 9 selects the bit line pair BLa(i)/NBLa(i) for the memory cell 4 in accordance with an externally input column address signal. Therefore, the bit line pair BLa(i)/NBLa(i) is connected electrically to the memory cell 4 and the data I/O circuit 12.
For a writing operation, data is input externally to the data I/O circuit 12, transferred through the bit line pair BLa(i)/NBLa(i), and written into the memory cell 4. For a reading operation, the stored data is read from the memory cell 4, transferred through the bit line pair BLa(i)/NBLa(i), and output from the data I/O circuit 12.
Next, the following is an explanation of the operation in which the defective memory cell 5 is specified by an externally input row address signal and column address signal.
Upon receiving a row address signal specifying the defective memory cell 5, the row decoder 3 compares the address indicated by the row address signal with the address of a defective memory cell row including the defective memory cell 5, which is indicated by the redundancy repair signal from the row redundancy repair signal generator 1. The two addresses are matched, so that the row decoder 3 selects the word line WLa(r) for the redundant memory cell 6 instead of the word line WLa(k) for the defective memory cell 5. This functional replacement of the defective memory cell row (including the defective memory cell 5) by the redundant memory cell row 7 (including the redundant memory cell 6) can repair the defective memory cell 5.
FIG. 9 is a block diagram showing the configuration of another conventional semiconductor memory 90A. The identical elements to those of the semiconductor memory 90 in FIG. 8 are denoted by the same reference numerals, and a detailed description will not be repeated. The semiconductor memory 90A differs from the semiconductor memory 90 in that the memory cell array 2 is divided into two memory cell arrays 2A, a row decoder 3 is located between the memory cell arrays 2A, and a row redundancy repair signal generator 1 is located opposite to the memory cell arrays 2A and the row decoder 3.
The semiconductor memory 90A is provided with a SRAM macro 80A. The SRAM macro 80A includes the two memory cell arrays 2A. The row decoder 3 is located between the memory cell arrays 2A. The row redundancy repair signal generator 1 is located outside the SRAM macro 80 and opposite to the row decoder 3 and the memory cell arrays 2A.
The SRAM macro 80A includes two data I/O circuits 12 that face the respective memory cell arrays 2A. Each of the data I/O circuits 12 is provided with a column decoder 9. A control circuit 11 is located between the data I/O circuits 12.
For a mass-storage SRAM, many memory cells are arranged in the direction of each memory cell row. Therefore, the word lines extending along the memory cell rows become longer, and a wiring load of the word lines is increased. This causes delay in signal transfer through the word lines, so that the operating speed required for access to a memory cell is decreased.
As shown in FIG. 9, when a memory cell array is divided into two memory cell arrays 2A, and the row decoder 3 is located between the memory cell arrays 2A, the word line length is reduced by half. Accordingly, this configuration can reduce the signal delay caused by an increase in wiring load of longer word lines.
The fuses provided in the row redundancy repair signal generator 1 are disconnected by a laser or the like. Therefore, it is not possible to form the signal wiring on the fuses. When the row redundancy repair signal generator 1 in FIG. 9 is located inside the SRAM macro 80A, the signal wiring should be arranged so as to avoid a region including the fuses, and thus the fuses interfere with the signal wiring. For this reason, the row redundancy repair signal generator 1 having the fuses is not located inside, but outside the SRAM macro 80A, as shown in FIG. 9.
The configuration that can achieve more flexibility in wiring of the word lines of a SRAM macro is disclosed by H. Shimizu et al., “A 1.4 ns Access 700 MHz 288 kb SRAM Macro with Expandable Architecture” ISSCC Digest of Technical Papers, pp. 190-191, February 1999.
As described above, however, the mass-storage SRAM includes many memory cells arranged in the direction of each memory cell row. Therefore, the lateral lengths of the individual memory cell arrays 2A are increased, so that a larger free space is formed on the right and left sides of the row redundancy repair signal generator 1 of the semiconductor memory 90A in FIG. 9.
In the configuration disclosed by the above document, a redundancy repair signal generator including fuses is separated from a SRAM macro and located at the periphery of a chip, and a signal line that connects the SRAM macro and the redundancy repair signal generator is necessary. Therefore, this configuration causes an area loss over the entire chip.